List of Tools Used and Developed
We list below the tools used and/or developed in the project, and provide links for more details on them.
TOPCASED (Airbus)
TOPCASED, the framework for integration of SPICES Tools. TOPCASED is an environment based on an N-tiers architecture centered on models, relies on meta-modelling to be able to manage any kind of model, and implements a plugin-based architecture the project tools providers will heavily rely on. The Development is based on existing popular open-source software (Eclipse.org platform, ATL, ...).
FAUST (Cetic)
As part of FAUST, a workbench targetting the development of systems having severe quality constraints, CETIC is focusing in the project on a component dealing with Architecture derivation from formalised requirements by following a "goal"-oriented approach. This component is currently being adapted to be integrated as Eclipse plugin.
OSATE (implemented by SEI, integrated with Topcased)
OSATE is a set of Eclipse plugins to front-end processing of AADL models. In particular, it allows to edition and performs error checking (conformance to the language) of AADL models, both in a textual and graphical fashion.
ADELE (Ellidiss Software)
ADELE provides a new AADL editor, with a new graphical layer.
MAST Schedulability analysis (University of Cantabria and THALES Communications)
University of Cantabria is engaged in investigating extensions of AADL so as to enrich the language's capabilities regarding scheduling analysis. THALES Communications is also considering the integration of scheduling analysis tools (MAST, from University of Cantabria) with the lightweight CCM component-framework.
SoftExplorer / OSExplorer (LESTER)
The intent is to provide a tool for power-consumption analysis, by taking into account the operating system behaviour. The link with AADL and SystemC will be provided.
AADS (University of Cantabria)
AADS targets the execution of AADL specifications in SystemC. It relies on a AADL architecture description to SystemC "equivalent" architecture. An intent is to integrate some existing library (multi-processors emulation with buses and memories) so as to enable performance analysis.
ADeS (Axlog Ingenierie)
ADeS is a tool to simulate the behavior of AADL models. The intent is to support the AADL behavioural annex, and to output graphical results of simulations. It comes as an eclipse plugin, and is freely available on the following link.
BIP (Verimag)
BIP implements the concept of components, and allows by inputing some components descriptions (ports and transitions) to simulate process states. It allows to verification of dynamic properties by state exploration by using the Observer concept.
BIP uses a native description language as input. Current work in the project includes the interfacing of BIP to AADL.
TINA (Féria)
TINA is a toolbox allowing to model, simulate, perform model checking of timed systems. In particular, it includes analysis of scheduling using the model checking techniques. It relies on a pivot language, named Fiacre, allowing to accomodate several modeling languages as input. Féria is currently involved in the integration of the toolbox with Topcased thanks to an AADL to Fiacre mapping. The integrated tool will allow as input AADL with behavioural extensions.
PathCrawler (CEA)
PathCrawler is a tool making static code analysis on C programs and generates vectors of datas allowing to realise a structural coverage of C programs.
As part of the project, the tool is specialised to be used for worst-cased execution time prediction: use of the datas for generation of tests combined with time measurements will allow the prediction of timings under some user-provided specification of usage conditions (e.g., ranges, ...)
AADL to CCM and CCM to AADL mappings (CEA)
CEA is developping some transformations engines to bridge AADL and CCM, based on a mapping jointly defined with Axlog Ingenierie and THALES Communications. The AADL to CCM mappings will be used in a top-down approach, for architectural mapping from models to implementation approach, in order to leverage the production of deployment and configuration artefacts for a CCM application. The reverse mapping will allow to reflect the actual component-based software in AADL, and the result of this related transformation will be the subject for analysis and verification tools.
CCM/IDL3 Embedded component-based framework (THALES Communications and CEA)
THALES Communications and CEA are jointly, based on earlier joint background in the microCCM component-based framework, developing the approach. Two aspects are currently investigated and prototyped:
- the integration of CCM with ARINC653 integrated modular avionics platforms on one hand
- the provision of middleware capabilities to reconfigurable hardware computing devices (FPGA), via the definition of some IDL to VHDL mapping, CCM components implementation rules in VHDL, and generation of communication code typically to be used between components on microprocessors and FPGA.
Code generation towards C and Ada (Airbus and K.U.Leuven DistriNet)
Airbus and K.U.Leuven DistriNet are developing code generators from AADL towards C and Ada. This will include generation of code for the structural elements and part of the behavioural elements.